1. Field of the Invention
The present invention relates to a reference potential generating circuit, a potential detecting circuit and a semiconductor integrated circuit device. More specifically, it relates to an intermediate potential generating circuit used in a semiconductor memory device, an internal potential detecting circuit for controlling an internal potential generating circuit used in a semiconductor memory device, and to a semiconductor integrated circuit device including the internal potential generating circuit.
2. Description of the Background Art
FIG. 81 is a schematic diagram showing a main structure of a dynamic random access memory (hereinafter referred to as a xe2x80x9cDRAMxe2x80x9d) which is one of semiconductor memory devices.
Referring to FIG. 81, the DRAM includes a bit line pair BL and /BL, word lines WL arranged in a direction orthogonal to the bit line pair BL and /BL, memory cells arranged corresponding to crossings between bit line pair BL and /BL and word lines WL, sense amplifiers SAn and SAp amplifying the voltage generated between the bit line pair BL and /BL, and a precharge circuit PC for precharging the bit line pair BL and /BL to an intermediate potential (xc2xd) Vcc of the power supply potential Vcc.
The memory cell MC includes a transfer gate TG and a capacitor C, and it is adapted such that when the potential at word line WL rises, data generated on the bit line pair BL and /BL is written to the capacitor C, or the data stored in capacitor C is read to bit line pair BL and /BL.
Sense amplifiers SAn and SAp are formed by an N channel sense amplifier SAn and a P channel sense amplifier SAp. N channel sense amplifier SAn includes cross coupled two N channel MOS transistors. P channel sense amplifier SAp includes two cross coupled P channel MOS transistors.
Precharge circuit PC supplies the intermediate potential (xc2xd) Vcc from precharge line VBL to bit line pair BL and /BL, and equalizes both potentials of the bit line pair BL and /BL in response to a control signal from a equalizing line EQ.
Reading operation of the DRAM will be described with reference to a timing chart of FIG. 82.
Before reading the data, bit line pair BL and /BL are precharged to the intermediate potential (xc2xd) Vcc. Then, when the potential of the word line WL increases to the boosted potential Vpp, the data in capacitor C is read to bit line BL through transfer gate TG, and therefore the potential of the bit line BL is shifted to the power supply potential Vcc or the ground potential Vss.
Then, when transfer gates S0 and /S0 (not shown) connected to sense amplifier driving lines SN and SP are rendered conductive, the potential of bit line BL attains to the ground potential Vss and the potential of bit line /BL attains to the power supply potential Vcc, for example.
As described above, in the DRAM, it is necessary to precharge the bit line pair BL and /BL to the intermediate potential (xc2xd) Vcc.
FIG. 83 is a schematic diagram showing the whole structure of a conventional intermediate potential generating circuit disclosed in U.S. Pat. No. 4,788,455.
Referring to FIG. 83, the intermediate potential generating circuit includes a reference potential generating stage 1 generating a reference potential Vref1, a reference potential generating stage 2 generating a reference potential Vref2, an output stage 3 responsive to these reference potential Vref1 and Vref2 for generating an intermediate potential (xc2xd) Vcc, and an output node 4.
Reference potential generating stage 1 includes a resistance element 1a, an N channel MOS transistor 1b, an N channel MOS transistor 1c and a resistance element 1d connected in series between a power supply node 100 to which the power supply potential Vcc is applied and a ground node 200 to which the ground potential Vss is applied. Reference potential generating stage 2 includes a resistance element 2a, a P channel MOS transistor 2b, a P channel MOS transistor 2c and a resistance element 2d connected in series between power supply node 100 and ground node 200. Output stage 3 includes an N channel MOS transistor 3a and a P channel MOS transistor 3b connected in series between power supply node 100 and ground node 200.
The reference potential Vref1 generated at node N1 is determined by a threshold voltage Vdn of diode connected N channel MOS transistor 1b. The reference potential Vref2 generated at node N2 is determined by the absolute value |Vtp| of the threshold voltage of diode connected P channel MOS transistor 2c. 
Therefore, at the gate electrode of P channel MOS transistor 3a in output stage 3, a voltage (xc2xd) Vcc+Vtn higher than the intermediate potential by the threshold voltage is applied. To the gate electrode of P channel MOS transistor 3b, a potential (xc2xd) Vccxe2x88x92|Vtp| lower than the intermediate potential by the absolute value of the threshold voltage is applied. Therefore, an intermediate potential (xc2xd) Vcc is generated as the output potential Vout at output node 4.
FIG. 85 shows the whole structure of an intermediate potential generating circuit shown in FIG. 4 of Japanese Patent Laying-Open No. 63-174115.
Referring to FIG. 85, the intermediate potential generating circuit includes reference potential generating stage 5 for generating two reference potentials, an output stage 3 and an output node 4. The output stage 3 is the same as that shown in FIG. 83.
The reference potential generating stage 5 of the intermediate potential generating circuit includes a P channel MOS transistor 5a having its gate electrode connected to ground node 200, a diode connected N channel MOS transistor 5b, a diode connected P channel MOS transistor 5c, and an N channel MOS transistor 5d having its gate connected to power supply node 100.
Similar to the one described above, in this intermediate potential generating circuit, a potential higher than the intermediate potential by the threshold voltage is applied to the gate electrode of N channel MOS transistor 3a in output stage 3, and a potential lower than the intermediate potential by the absolute value of the threshold voltage is applied to the gate electrode of P channel MOS transistor 3b, and hence the intermediate potential (xc2xd) Vcc is generated at the output node 4.
FIG. 86 is a schematic diagram showing an example of a boosted potential detecting circuit used in a DRAM. The boosted potential Vpp is supplied as power supply to a word driver driving a word line, for example. Referring to FIG. 86, the boosted potential detecting circuit includes P channel MOS transistors 6a to 6d connected in series between a detecting node 804 and ground node 200, and an inverter 7. Transistors 6a to 6d are each diode connected. Inverter 7 consists of P channel MOS transistor 7a and an N channel MOS transistor 7b. 
In the boosted potential detecting circuit, when the potential at node NA is lower than the logical threshold value of inverter 7, an enable signal GE at the H (logic high) level is generated at output node 801. In response to the H level enable signal GE, the boosted potential generating circuit (not shown) is activated. Meanwhile, when the potential at node NA becomes higher than the logical threshold value of inverter 7, an enable signal GE at the L (logic low) level is generated at output node 801. In response to the L level enable signal GE, the boosted potential generating circuit is inactivated.
However, in the intermediate potential generating circuit shown in FIG. 83, in order to reduce through current flowing from power supply node 100 to ground node 200 in reference potential generating stage 1, the values of resistance elements 1a and 1d must be set as high as several Mxcexa9. The same applies to reference potential generating stage 2.
In contrast, in the DRAM, in order to increase the speed of signal transmission, interconnection material having smaller resistance value per unit length tends to be used. Therefore, when such a material that has small resistance value per unit length is used for forming the resistance elements 1a, 1d, 2a and 2d, the layout area would be considerably large.
FIG. 84 is a graph showing time change of potentials at various nodes immediately after power on of the intermediate potential generating circuit shown in FIG. 83.
Referring to FIG. 84, when the power is turned on, initially the potential at power supply node 100 gradually increases from 0V to Vcc. The dotted line in the graph represents half the potential of the power supply node 100.
Since resistance element 1a of reference potential generating stage 1 has very large value, the potential at node N1 does not rapidly increase even when the potential at power supply node 100 increases. Further, since resistance element 2a in reference potential generating stage 2 also has large value, the potential at node N2 does not rapidly increase, either. Therefore, it takes very long for the output potential Vout to reach the intermediate potential (xc2xd) Vcc.
The current I flowing in reference potential generating stage 5 of the intermediate potential generating circuit shown in FIG. 85 is represented by the following equation (1):
I=xcex2p(Vccxe2x88x92Vtn) (Vccxe2x88x92Vtp)xe2x80x83xe2x80x83(1)
where xcex2p represents the degree of movement of holes in P channel MOS transistor. Vtn represents the threshold voltage of the N channel MOS transistor. Vtp represents the threshold voltage of the P channel MOS transistor.
In the intermediate potential generating circuit, when the current I represented by the equation (1) flows in reference potential generating stage 5, the intermediate potential (xc2xd) Vcc is generated at output node 4. Therefore, the current I does not have the desired value unless the threshold voltages Vtn and Vtp are set accurately, causing deviation of the output potential Vout from the intermediate potential (xc2xd) Vcc.
FIG. 3 is a graph showing a result of simulation of output potential Vout with respect to the deviation of the threshold voltage Vtn, when the power supply potential Vcc is set to 2.5V. As is apparent from the graph, when the threshold voltage Vtn deviates, the output potential Vout varies significantly.
In the boosted potential detecting circuit shown in FIG. 86, when the power supply potential Vcc fluctuates, the logical threshold value of inverter 7 varies, and therefore the detection level of the boosted potential detecting circuit is not stable. Further, since the boosted potential Vpp is applied to node NA through diode connected three transistors 6a to 6c, the detection level of the boosted potential detecting circuit also varies when the operational temperature varies. This is because the threshold voltage of the transistor varies when the operational temperature changes. Since three transistors are connected in series in the boosted potential detecting circuit, the fluctuation of the threshold voltage is amplified three times.
An object of the present invention is to provide a reference potential generating circuit which is capable of generating more stable reference potential.
Another object of the present invention is to provide a reference potential generating circuit capable of generating a desired reference potential accurately.
A still further object of the present invention is to provide a reference potential generating circuit capable of generating a desired reference potential quickly after power on.
A still further object of the present invention is to provide a reference potential generating circuit of which layout area is sufficiently small.
A still further object of the present invention is to provide an internal potential detecting circuit having a stable detection level.
A still further object of the present invention is to provide an internal potential detecting circuit of which detection level does not fluctuate with the fluctuation of the power supply potential.
A still further object of the present invention is to provide an internal potential detecting circuit of which detection level does not fluctuate with the fluctuation of operational temperature.
The reference potential generating circuit according to one aspect of the present invention is for generating a reference potential between a first potential and a second potential, and it includes an output node, a first transistor of a first conductivity type, for example, an N channel MOS transistor, a first transistor of a second conductivity type, for example a P channel MOS transistor, a second transistor of the second conductivity type, a second transistor of the first conductivity type, a third transistor of the first conductivity type and a third transistor of the second conductivity type. The aforementioned reference potential is generated at the output node. The aforementioned first transistor of the first conductivity type has one conduction electrode connected to the output node, and another conduction electrode connected to a first node to which a third potential is applied. The first transistor of the second conductivity type has one conduction electrode connected to the output node, and another conduction electrode connected to a second node to which a fourth potential is applied. The second transistor of the second conductivity type has one conduction electrode connected to a third node to which the first potential is applied, another conduction electrode connected to a control electrode of the first transistor of the first conductivity type, and a control electrode connected to the output node. The second transistor of the first conductivity type has one conduction terminal connected to a fourth node to which the second potential is applied, another conduction electrode connected to a control electrode of the first transistor of the second conductivity type, and a control electrode connected to the output node. The third transistor of the first conductivity type has one conduction electrode, and another conduction electrode and a control electrode connected to each other and to said another conduction electrode of the second transistor of the second conductivity type. The third transistor of the second conductivity type has one conduction electrode connected to the aforementioned one conduction electrode of the third transistor of the first conductivity type, and another conduction electrode and a control electrode connected to each other and to the aforementioned another conduction electrode of the second transistor of the first conductivity type.
The reference potential generating circuit according to another aspect of the present invention includes an output node, a transistor of a first conductivity type, for example a P channel MOS transistor, an output resistance element, and a control potential generating circuit. A reference potential is generated at the output node. The transistor of the first conductivity type has one conduction electrode connected to a first node to which the first potential is applied, and another conduction electrode connected to the aforementioned output node. The output resistance element is connected between the output node and a second node to which a second potential is applied. The control potential generating circuit includes a first path from a third node to which a third potential is applied to a fourth node to which a fourth potential is applied; a second path from a fifth node to which a fifth potential is applied to a sixth node to which a sixth potential is applied; a first current mirror circuit responsive to a current flowing through the first path for controlling current flowing through the second path; a second current mirror circuit responsive to the current flowing through the second path for controlling the current flowing through the first path; a control node positioned in the first path between the first and second current mirror circuits and connected to the control electrode of the transistor of the first conductivity type; a first resistance element connected in the first path between the control node and the first current mirror circuit; and a second resistance element connected in the first path between the second current mirror circuit and the fourth node.
According to a still further aspect of the present invention, the potential detecting circuit detects a potential to be detected, and determines whether or not the detected internal potential has reached a prescribed detection level, and it includes an output node, a reference current supplying circuit, a detection node, and comparing current supplying circuit. The reference current supplying circuit supplies a prescribed reference current to the output node. To the detection node, a potential to be detected is applied. The comparing current supplying circuit supplies a comparing current to the output node, in response to the potential applied to the detection node. At this time, when a positive reference current is applied to the output node, a negative comparing current is supplied to the output node. Conversely, when a negative reference current is supplied to the output node, a positive comparing current is applied to the output node.
Therefore, in the reference potential generating circuit described above, the reference potential generated at the output node is fed back to the control electrode of the second transistor of the second conductivity type and the control electrode of the second transistor of the first conductivity type, and therefore even when the reference potential varies, it quickly returns to the original value. Therefore, a more stable reference potential can be generated. When the power is turned on, initially the potential at the output node is 0V. This potential is also fed back to the control electrode of the second transistor of the second conductivity type and the control electrode of the second transistor of the first conductivity type. Therefore, the potential at the output node quickly attains the reference potential. Further, the second transistor of the second conductivity type and the third transistor of the first conductivity type are arranged in symmetry with respect to the second transistor of the first conductivity type and the third transistor of the second conductivity type. Therefore, the potential at the node at which one conduction electrode of the third transistor of the first conductivity type and one conduction electrode of the third transistor of the second conductivity type are connected to each other assumes exactly the intermediate potential between the first and second potentials. Therefore, an accurate intermediate potential can be generated as the reference potential. Further, since the second transistor of the second conductivity type and the second transistor of the first conductivity type are used for supplying current to the third transistor of the first conductivity type and the third transistor of the second conductivity type, the layout area can be reduced as compared with an example employing a resistance element.
In the reference potential generating circuit according to another aspect of the present invention, when the value of the first resistance element is appropriately changed, the control potential supplied to the control electrode of the transistor of the first conductivity type varies in response to the change of the resistance value, and therefore current flowing through the output resistance element also varies. Therefore, the desired reference potential can be generated at the output node.
In the internal potential detecting circuit according to the still further aspect of the present invention, the relation of magnitude of the reference current and a comparing current varies in response to the internal potential applied to the detection node. Therefore, when the internal potential attains to the detection level, the potential at the output node changes.